Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

Our client is a global technology leader specializing in advanced memory and storage solutions that power next-generation computing and data-driven applications. With strong expertise in semiconductor innovation, the organization develops high-performance memory technologies across DRAM, NAND, and storage platforms for applications spanning data centers, artificial intelligence, mobile devices, client computing, and intelligent edge ecosystems.

Driven by a commitment to technology advancement, operational excellence, and customer-centric innovation, the company plays a significant role in enabling modern digital infrastructure and compute-intensive workloads worldwide.

Responsibilities:

• Develop and optimize assembly processes for advanced packaging technologies, including wafer-level packaging, Chip-on-Wafer (CoW), and Chip-to-Wafer (C2W) die stacking.
• Improve product quality, yield, productivity, and manufacturing cost.
• Drive process management projects supporting future technology nodes.
• Evaluate, qualify, and implement new equipment and materials.
• Establish process parameters for semiconductor manufacturing equipment.
• Ensure robust quality through process monitoring, inspection, testing, SPC, DOE, and defect analysis.
• Use data analytics to establish advanced process controls and identify improvement opportunities.
• Collaborate with Package Integration, Assembly Engineering, Front-End Wafer Fab, Assembly/Test Engineering, Product Engineering, and Global Quality teams.
• Support seamless transition from product development through qualification into High Volume Manufacturing (HVM).
• Provide Process of Record (POR) and Model of Record (MOR) documentation.

Requirements:

• B.S./M.S./Ph.D. (or equivalent) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.
• 2+ years of semiconductor process development or equipment evaluation experience, preferably in wafer bonding, die stacking, or advanced packaging.
• Proficiency in Python, R, and SQL.
• Experience with Visual Basic for automation and tool integration.
• Knowledge of E3, FDC (Fault Detection and Classification), and RMS (Recipe Management System).
• Strong data analytics capability supporting SPC, DOE, defect analysis, and dashboards.
• Strong understanding of semiconductor process flows, yield, performance, and reliability.
• Strong problem-solving and root-cause analysis skills.
• Ability to work effectively under aggressive timelines and limited resources.