The position will involve working with a very experienced physical design team of a CPU core and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power, and other design requirements for our client next-generation processors in a fast-paced environment on cutting edge technology.
Engineer with a good attitude who seeks new challenges and has good analytical and communication skills. The candidate needs to have the ability and desire to learn quickly and should be a good team player.
15+ years’ experience in ASIC Design with relevant Physical Design Skills
Minimum BSEE/CE, or equivalent degree, Masters is preferred.
Must have prior experience leading Physical Design teams of at least 10 members
Excellent analytical and problem-solving skills along with attention to details.
Strong written and verbal communication, Time Management and Presentation Skills.
Must be a self-starter, and able to drive independently and efficiently challenging and time critical tasks to on-time completion.
Forward looking and dependable leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper.
Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, mut have strong technical management skills and provide a positive influence on team morale and culture
Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics required.