Member of Technical Staff for SOC Verification

Posted 2 month

Skills

PCIe DDR SystemVerilog Universal Verification Methodology (UVM) System Verification

Functions

Information Technology

Industries

Information Technology and Services

Locations

Bengaluru India

Seniority

Mid-Senior

Description

Responsibilities:

Knowledge in IP/SOC Design Verification Methodologies.
Strong in System Verilog (SV), Methodology (UVM), Constrained random generator, Coverage is driven verification, Gate-level simulations.
Expertise in domains like DDR/PCI-E/10G Ethernet will be desirable.
Knowledge in processor-based systems verification will be an advantage.
Knowledge of CPU/DSP architectures, SOC Verification, Low power verification will be desirable.
Good knowledge of scripting languages like PERL, Shell, Python, TCL.
Multiple positions are open.

Requirements:

Exp Level: 8 Years to 12 Years.
Passion for coding, learning, and collaboration.
Good communication skills have initiative and seek responsibility.
Knowledge of operating systems and/or computer architecture.
Familiarity with computer hardware.
Master’s in Digital Systems / VLSI / Embedded Systems with focus on Design/Verification and good knowledge of Verilog/System Verilog.

Similar to this job

Posted 2 month

Posted 2 month

Posted 2 month

Posted 2 month

Posted 2 month